1. Field of the Invention
The present invention relates to a liquid crystal display device and a method for producing the same.
2. Description of the Related Art
One known type of liquid crystal display device is an active matrix liquid crystal display device including an active matrix substrate including a plurality of pixel electrodes arranged in a matrix and a counter substrate including a counter electrode. The active matrix substrate and the counter substrate are located so as to hold a liquid crystal layer therebetween. In such a liquid crystal display device, the active matrix substrate usually has thin film transistors (TFT) respectively for applying a voltage to the pixel electrodes.
Such an active matrix liquid crystal display device is often used as one element of a projector apparatus. However, when a liquid crystal display device is used for a projector apparatus, the liquid crystal display device is exposed to a high intensity of light.
When the TFTs provided on the active matrix substrate of the liquid crystal display device are exposed to the high intensity of light, there is an undesirable possibility that a leak current is generated in the TFTs. When this occurs, the quality of images displayed by the liquid crystal display device may be lowered due to, for example, reduction of contrast of the liquid crystal display device and generation of crosstalk.
In order to solve these problems, it is known to provide a light shielding layer on the active matrix substrate so as to prevent light from being incident on the TFTs.
For example, Japanese Laid-Open Publication No. 2001-242443 discloses a liquid crystal display device which includes an active matrix substrate including an upper light shielding layer above the TFTs and below the pixel electrodes and a lower light shielding layer below the TFTs.
With reference to FIGS. 37A through 39, a conventional liquid crystal display device 1000 will be described. The following description will be presented regarding an area of a liquid crystal display device corresponding to one TFT for the sake of simplicity.
FIGS. 37A and 37B are each a schematic plan view of a portion of an active matrix substrate 110 of the liquid crystal display device 1000 where one gate line 112 and one signal line 113 cross each other.
FIGS. 37A and 37B each show only one gate line 112 and one signal line 113, but the active matrix substrate 110 includes a plurality of gate lines 112 and a plurality of signal lines 113.
The plurality of gate lines 112 are generally provided above a transparent plate 111 (FIG. 38) of the active matrix substrate 110 and parallel to each other. The plurality of signal lines 113 are generally provided above the transparent plate 111 and parallel to each other. The gate lines 112 and the signal lines 113 generally cross each other.
FIGS. 37A and 37B represent the same liquid crystal display device 1000 such that the positions of light shielding layers are clear as explained below.
In FIG. 37A, an upper light shielding layer 118 provided above a TFT 160 is hatched so as to clearly show the position thereof. The upper light shielding layer 118 acts to prevent light from being incident on the TFT 160 from above the active matrix substrate 110.
In FIG. 37B, a lower light shielding layer 116 provided below the TFT 160 is dotted so as to clearly show the position thereof. The lower light shielding layer 116 acts to prevent light from being incident on the TFT 160 from below the active matrix substrate 110.
As shown in FIG. 37A, the upper light shielding layer 118 is provided so as to cover a first contact hole 127, the gate line 112, the signal line 113, a portion of a polycrystalline silicon (Si) layer 131, a portion of a capacitance electrode 115 and a portion of the TFT 160.
As shown in FIG. 37B, the lower light shielding layer 116 is provided so as to cover a portion of the gate line 112, the signal line 113, the first contact hole 127, a second contact hole 128, a third contact hole 129a, a fourth contact hole 132a, the polycrystalline silicon (Si) layer 131, and the TFT 160.
As described above, the active matrix substrate 110 includes the plurality of gate lines 112 and the plurality of signal lines 113 crossing each other perpendicularly.
In an area surrounded by two gate lines 112 and two signal lines 113, a pixel electrode 114 is provided.
The capacitance electrode 115 is provided in the vicinity of the gate line 112 so as to be parallel to the gate line 112. The capacitance electrode 115 is formed such that a width of the capacitance electrode 115 is larger than the width of the gate line 112.
The polycrystalline silicon layer 131 of n-type used as a part of the TFT 160 is provided below a portion of the signal line 113 which crosses the gate line 112. The width of the polycrystalline silicon layer 131 is smaller than the width of the signal line 113. The polycrystalline silicon layer 131 includes a channel region 131a, a lightly doped drain (LDD) region (N−) 131d provided between the channel region 131a and the first contact hole 127, and a lightly doped drain (LDD) region (N−) 131e provided between the channel region 131a and the second contact hole 128.
The polycrystalline silicon layer 131 extends along the signal line 113 so as to cross the gate line 112. The polycrystalline silicon layer 131 has a branch portion extending so as to be below the capacitance electrode 115. The branch portion below the capacitance electrode 115 has a width smaller than the width of the capacitance electrode 115.
The lower light shielding layer 116 is provided below the polycrystalline silicon layer 131. The width of the lower light shielding layer 116 is larger than the width of the polycrystalline silicon layer 131. The lower light shielding layer 116 is provided so as to cover the polycrystalline silicon layer 131 from below and to cover the gap between the capacitance electrode 115 and the gate line 112 in the vicinity thereof.
In the first contact hole 127, a source electrode 133 of the TFT 160 is provided.
In the second contact hole 128, a drain electrode 134 of the TFT 160 is provided. FIG. 38 is a schematic cross-sectional view of the liquid crystal display device 1000 taken along line A—A of FIGS. 37A and 37B, and FIG. 39 is a schematic cross-sectional view of the liquid crystal display device 1000 taken along line B—B of FIGS. 37A and 37B.
As shown in FIGS. 38 and 39, the liquid crystal display device 1000 includes the active matrix substrate 110 and a counter substrate 140, and a liquid crystal layer 150 interposed between the active matrix substrate 110 and the counter substrate 140.
The counter substrate 140 includes a transparent plate 141 formed of quartz glass, a transparent electrode 142 provided on the transparent plate 141, and an alignment layer 143 provided on the transparent electrode 142.
The active matrix substrate 110 includes the transparent plate 111 formed of quartz glass.
The lower light shielding layer 116 is provided on the transparent plate 111, and a first interlayer insulating layer 117 is provided on the transparent plate 111 so as to cover the lower light shielding layer 116.
The polycrystalline silicon layer 131 is provided on the first interlayer insulating layer 117, and a second interlayer insulating layer (gate insulating layer) 119 is provided on the first interlayer insulating layer 117 so as to cover the polycrystalline silicon layer 131.
The gate line 112 and the capacitance electrode 115 are provided on the second interlayer insulating layer 119.
A third interlayer insulating layer 121 is provided on the second interlayer insulating layer 119 so as to cover the gate line 112 and the capacitance electrode 115.
The first contact hole 127 and the second contact hole 128 are formed in the second interlayer insulating layer 119 and the third interlayer insulating layer 121.
The first contact hole 127 is filled with a conductive material which is the same as the material of the signal line 113 so as to form the source electrode 133 of the TFT 160. The source electrode 133 electrically connects the signal line 113 and a source region of the polycrystalline silicon layer 131.
The signal line 113 is provided on the third interlayer insulating layer 121 in a prescribed pattern.
The second contact hole 128 is filled with a conductive which is the same as the material of a connecting electrode 126 so as to form the drain electrode 134 of the TFT 160. The drain electrode 134 electrically connects the connecting electrode 126 and a drain region of the polycrystalline silicon layer 131.
The connecting electrode 126 is formed on the third interlayer insulating layer 121 in a rectangular pattern.
A first flat layer 125 is provided on the third interlayer insulating layer 121 so as to cover the signal lines 113 and the connecting electrode 126. The upper light shielding layer 118 (black matrix) is provided on the first flat layer 125. The upper light shielding layer is formed of a conductive material.
The third contact hole 129a is formed in the first flat layer 125 covering the connecting electrode 126. The upper light shielding layer 118 is electrically connected to the connecting electrode 126 via the third contact hole 129a. 
A second flat layer 129 is provided on the first flat layer 125 so as to cover the upper light shielding layer 118.
The fourth contact hole 132a is formed in the second flat layer 129 in the vicinity of the third contact hole 129a. 
The plurality of pixel electrodes 114 are provided on the second flat layer 129, and each pixel electrode 114 is connected to the upper light shielding layer 118 via the fourth contact hole 132a. 
An alignment layer 136 is provided on the second flat layer 129 so as to cover the plurality of pixel electrodes 114.
The active matrix substrate 110 and the counter substrate 140 are located such that alignment layer 136 of the active matrix substrate 110 and the alignment layer 143 of the counter substrate 140 are opposed to each other with a prescribed distance therebetween. The liquid crystal layer 150 is provided between the alignment layer 136 and the alignment layer 143. Thus, the liquid crystal display device 1000 is completed.
The liquid crystal display device 1000 is produced in the following manner.
First, on the transparent plate 111 formed of quartz glass, a polycrystalline silicon layer doped with P (phosphorus) and a WSi layer are sequentially formed and patterned, thereby forming the lower light shielding layer 116.
Next, an SiO2 layer is formed by, for example, CVD on the entire surface of the transparent plate 111 so as to cover the lower light shielding layer 116, thereby forming the first interlayer insulating layer 117.
A polycrystalline silicon layer is formed by, for example, CVD on the entire surface of the first interlayer insulating layer 117, and patterned into a prescribed shape, thereby forming the polycrystalline silicon layer 131.
Another SiO2 layer is formed on the entire surface of the first interlayer insulating layer 117 by, for example, CVD so as to cover the polycrystalline silicon layer 131, and patterned as prescribed, thereby forming the second interlayer insulating layer (gate insulating layer) 119.
A polycrystalline silicon layer doped with P and a WSi layer are sequentially formed on the entire surface of the first interlayer insulating layer 117 so as to cover the second interlayer insulating layer 119, and patterned as prescribed, thereby forming the gate line 112 and the capacitance electrode 115. The capacitance electrode 115 is for a storage capacitance device.
Then, an SiO2 layer, for example, is formed on the entire surface of the second interlayer insulating layer 119 so as to cover the resultant laminate by, for example, CVD, thereby forming the third interlayer insulating layer 121.
Prescribed portions of the second interlayer insulating layer 119 and the third interlayer insulating layer 121 are etched, thereby forming the first contact hole 127 and the second contact hole 128.
The formation of the first contact hole 127 and the second contact hole 128 in the second interlayer insulating layer 119 and the third interlayer insulating layer 121 exposes a portion of the polycrystalline silicon layer 131 from the first contact hole 127 and the second contact hole 128.
A WSi layer or an Al layer and a WSi layer are sequentially formed on the third interlayer insulating layer 121 so as to cover the resultant laminate, and patterned as prescribed, thereby forming the source electrode 133 and the drain electrode 134 of the TFT 160, the connecting electrode 126 and the signal line 113.
Then, an SiO2 layer is formed by, for example, atmospheric pressure CVD on the entire surface of the third interlayer insulating layer 121 so as to cover the resultant laminate. An SiN layer, for example, is formed by, for example, plasma CVD on the SiO2 layer, and patterned as prescribed.
An SiO2 layer is formed by, for example, plasma CVD using TEOS (tetraethylorthosilicate) as a material gas so as to cover the patterned SiN layer. At this point, the thickness of the SiO2 layer is, for example, about 2500 nm.
The SiO2 layer is polished by CMP (chemical mechanical polishing) to a thickness of, for example, 2200 nm, and thus flattened. The post-flattening step level can be 0.5 μm or less, or even 0.1 μm or less depending on the conditions.
A prescribed portion of the flattened SiO2 layer is etched, thereby forming the first flat layer 125 having the third contact hole 129a. 
Then, a Ti layer is formed by, for example, vapor deposition or sputtering on the first flat layer 125 so as to cover the fourth contact hole 132a, and patterned as prescribed, thereby forming the upper light shielding layer 118. The upper light shielding layer 118 is conductive.
Then, the second flat layer 129 is formed by SOG (spin-on-glass) on intermediate layer (not shown) so as to cover the upper light shielding layer 118. The second flat layer 129 may be formed by CMP. The intermediate layer is formed of an SiO2 layer by plasma CVD using, for example, TEOS as a material gas.
A prescribed portion of the second flat layer 129 is etched, thereby forming the fourth contact hole 132a. 
An ITO layer is formed on the entire surface of the second flat layer 129 so as to cover the fourth contact hole 132a to a thickness of, for example, about 70 nm, and patterned as prescribed, thereby forming pixel electrodes 114.
In this manner, the active matrix substrate 110 is produced.
The counter substrate 140 is formed by forming the transparent electrode 142 on the entire surface of the transparent plate 141, and then forming the alignment layer 143 on the entire surface of the transparent electrode 142.
The active matrix substrate 110 and the counter substrate 140 are located such that the alignment layers 136 and 143 thereof are opposed to each other with a prescribed distance therebetween. A liquid crystal layer 150 is provided between the alignment layers 136 and 143. Thus, the liquid crystal display device 1000 is produced.
In the liquid crystal display device 1000 having such a structure, the upper light shielding layer 118 shields light from being incident on the TFT 160 of the active matrix substrate 110 after being incident on and passing through the counter substrate 140. The lower light shielding layer 116 shields light from being incident on the TFT 160 after being incident on a bottom surface of the transparent plate 111 of the active matrix substrate 110 and passing through the transparent plate 111, and also light from being incident on the TFT 160 after passing through the transparent plate 111 and reflected by the optical system (not shown).
In order for the upper light shielding layer 118 and the lower light shielding layer 116 to shield light from being incident on the TFT 160 with certainty, the upper light shielding layer 118 and the lower light shielding layer 116 are formed so as to be larger than the TFT 160.
However, when the upper light shielding layer 118 and the lower light shielding layer 116 become larger, the area of the opening regions of the liquid crystal layer 150 through which the light is transmitted becomes smaller, which reduces the numerical aperture.
When the sizes of the upper light shielding layer 118 and the lower light shielding layer 116 are set to be appropriate for obtaining a sufficient numerical aperture, light obliquely incident on the active matrix substrate 110, light incident on the bottom surface of the transparent plate 111, light reflected by the optical system and the like cannot be shielded with certainty. In addition, light is multiple-reflected between the upper light shielding layer 118 above the TFT 160 and the lower light shielding layer 116 below the TFT 160, which may undesirably result in light being incident on the TFT 160.